1. Field of the Invention
This invention relates to a method of forming shallow semiconductor device isolation trenches.
2. Description of the Prior Art
Semiconductor integrated circuit devices, especially very large scale integrated circuits ("VLSI"), such as high density memory products like Dynamic Random Access Memories are becoming more and more dense, i.e., more transistors in a given area. These products are continually requiring smaller and smaller transistors. In high density VLSI's, it is necessary to electrically isolate adjoining transistors. Isolation trenches filled with a dielectric, normally Silicondioxide, are presently being used to isolate adjacent transistors and other devices which require isolation. In the state of the art VLSI's, the minimum feature size has reached submicron level. It is, therefore, extremely desirable to make isolation trenches as small and as reliable as possible.
Shallow trench isolation has been proposed as a means to achieve reliable submicron isolation trenches. In CMOS technology, an inherent difficulty in obtaining adequate N-Channel MOSFET behavior when using trench isolation is controllability of current conduction along the trench sidewalls. Higher dopant concentration on the trench sidewalls compared to the trench top and or bottom will generally suppress early transistor turn-on by increasing the threshold voltage of the parasitic edge transistor.
In CMOS Technology, P-type substrates containing N-wells therein are commonly used. NMOSFETS are formed in the P-substrate while the PMOSFETS are formed in the N-wells. In a CMOS device, NMOSFETS and PMOSFETS are isolated from each other by a shallow trench which isolates the P-substrate and the N-well. Likewise, isolation trenches separate NMOSFETS from NMOSFETS, and PMOSFETS from PMOSFETS on the same substrate. However, any sidewall dopant used must be absent from the portion of the trench which is in the N-well. The two trench sidewalls which define width dimensions of a MOSFET also act as parasitic transistors electrically connected in parallel with the normal planar transistor. For the NMOSFET, these parasitic sidewall transistors have a lower threshold voltage (Vt) than the planar transistor. This Vt difference is due to a higher fixed positive charge generated at the silicon substrate and silicon dioxide sidewall interface and/or an unfavorable P-dopant (generally boron) segregation constant. The latter factor results in the surface P-type dopant concentration being depressed below its bulk value during the trench oxidation step. For PMOSFETS, the sidewall parasitic devices have a higher Vt (larger negative value) than the planar device as the effect of higher fixed positive charge and a favorable segregation constant of phosphorus will act t increase the threshold voltage.
A configuration without sidewall doping would upset the off state of the NMOSFET, i.e., when biased with a gate voltage below Vt. The lower Vt of the parasitic sidewall transistors provides a parallel conduction path which allows undesirable excess current to flow from source to drain terminals in this off state. To counteract this problem, the Vt of parasitic sidewall NMOSFETS must be increased. A practical means of achieving this is to dope the trench sidewalls with the P-type dopant by some means.
The level of transistor off-current is especially important in circuits containing dynamic design. It may be possible to reduce the level of off-current leakage by two orders of magnitude with inclusion of sidewall doping. In addition, sidewall doping may be beneficial in suppressing the inverse narrow width behavior of threshold voltage often observed in shallow trench isolation.
The shape of the trench corners is also of concern for thin gate oxide reliability. Round active area corners are desired to minimize electric field intensification and/or oxide thinning at these corners. Both of these phenomena contribute to high oxide leakage current of transistors built with shallow trench isolation. Rounding of the trench corners is commonly done by additional thermal oxidation steps. The present invention, however, enables one to achieve the desired degree of roundness without any additional oxidation step.
For the foregoing reasons, in the art of making semiconductor devices, it is very desirable to make shallow trenches. Various trench sidewall doping methods for shallow trenches have been proposed. However, each of these methods has drawbacks relating to either the controllability of the dopant or higher manufacturing costs because specialized equipment may be required. For example, Fuse et al., "A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow Width Effect," IEEE Transaction Electron Devices, February 1987, discloses implanting trench sidewalls using large-tilt angle of the ion beam. Large-tilt angle is not easily implemented on commercially available implant machines because they are usually preset at a 5-9 degree beam angle incident to the silicon wafer surface to reduce ion channeling. Implantation of vertical trench sidewalls done at this low incident beam angle results in only the lower portion of the trench sidewall receiving dopant. To ensure symmetrical device behavior, all four sides of the trench must be implanted at the desired angle. The wafer must be rotated three times, which results in lower throughput during manufacturing. Although ion implanters with variable tilt angles have recently become commercially available, they are more expensive than the conventional fixed angle ion implanters, and they still require repositioning or rotation of wafers during ion-implantation of the regions such as trench sidewalls. Shibata et al., "A Simplified Box (Buried--Oxide) Isolation Technology of Megabit Dynamic Memories," IEDM Technical Digest, 1983, utilizes tapered trench sidewall profiles which allows the conventional low incident angle of the ion beam to implant a greater portion of the trench sidewall. But, when tapered trench sidewalls are used, it is difficult to maintain consistent trench profiles during subsequent resist-etch processing steps. Also, the transistor width is decreased because of resist erosion during the trench etch. Furthermore, vertical trench sidewalls are more desirable because they enable narrower trenches and thus providing higher density.
Diffusion from CVD doped oxide and/or doped polysilicon are methods which dope the entire trench sidewall. The film can be either boro-silicate glass (BSG) or in-situ boron doped polysilicon. The film is deposited over the entire wafer surface, i.e. trench bottom and sidewalls and usually must be removed using a conventional resist patterning/etch from locations where no dopant is desired After heat treatment, which transfers dopant into the trench sidewall, the diffusion source is again removed so that normal processing can continue. In the case of the doped oxide diffusion source, precise control of dopant in the oxide is critical to controlling silicon surface doping concentration after drive-in. This degree of control is often not achievable with conventional low pressure chemical vapor deposition (LPCVD) of oxide.
Diffusion from a doped polysilicon source suffers from difficulty of removing the polysilicon after drive-in since the polysilicon must be directly deposited on the trench which is formed in a single crystal silicon wafer. Complex chemical etchants are required to remove the polysilicon but not the crystal silicon.
Doping using electron cyclotron resonance plasma has been used in the art, but it is presently considered impractical due to the unavailability of equipment and/or high implementation cost.
The present invention overcomes a number of disadvantages of the prior art methods by providing a method of making shallow isolation trenches having properly doped sidewalls, wherein the desired doping of the trench sidewalls and the bottom surface is done by selectively forming a properly doped silicon (polysilicon or epitaxial) layer thereon. Oxidation of the trenches, dielectric fill and etch back of the wafer, and the formation of the N-Channel and P-Channel MOSFETS are done by conventional methods.